1. Field Of The Invention
This invention relates to flash electrically-erasable programmable read only memory arrays and, more particularly, to circuitry for protecting such arrays from storage errors caused by accessing the array.
2. History Of The Prior Art
Modern computer systems make extensive use of long term memory. One form of long term storage used in computers is flash electrically-erasable programmable read-only memory (flash EEPROM). A flash EEPROM memory array is an EPROM memory array which may be electrically erased and reprogrammed in place. A flash EEPROM memory array includes a large plurality of floating-gate field effect transistors arranged as memory cells in typical row and column fashion with circuitry for accessing the individual cells and placing the memory transistors of those cells in one of two memory conditions. A flash memory cell, like a typical EPROM cell retains information when power is removed from the array.
Flash EEPROM memory has a number of characteristics which adapt it to use as long term memory. It is light in weight, occupies very little space, and consumes less power than electro-mechanical disk drives. More importantly, it is especially rugged. It will withstand without adverse effects repeated drops each of which would destroy a typical electro-mechanical hard disk drive.
It is well known that when EEPROM cells are used in a memory array, circuitry is sometimes required to electrically isolate the cells one from another. This may be needed, for example, to permit the reading, programming, or erasing of a cell without disturbing the programming of adjacent cells. Examples of such circuitry are illustrated in U.S. Pat. No. 5,065,364, entitled Apparatus for Providing Block Erasing In A Flash EEPROM, Atwood et al, issued Nov. 12, 1991, and assigned to the assignee of the present invention.
Prior art memory arrays using flash EEPROM cells which utilize electrical isolation were designed to handle data furnished in eight bit (byte) increments. Flash EEPROM memory arrays, like other forms of long term memory, must read and write data which a host may desire or furnish in both byte or word form. Consequently, such prior art arrays handled data furnished in word form as two separate bytes, taking the time necessary to deal with the bytes independently. Recently, flash EEPROM memory arrays have been enlarged and are now able to handle data furnished in sixteen bit (word) increments. In providing circuitry to allow reading and writing to occur on both byte and word basis, it has been discovered that the electrically-isolation arrangements which protected flash EEPROM memory arrays storing only eight bits of data do not sufficiently protect flash EEPROM memory arrays storing sixteen bits which are also able to read and write data in eight bit groups.